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S E M I C O N D U C T O R, I N C .
TQ8032
64 D0 - 31 Input Buffers 32 x 32 Crosspoint Switch Matrix 64 Output Buffers O0 - 31
800 Megabit/sec 32x32 Digital ECL Crosspoint Switch
CONFIGURE
32 5-Bit Configuration Latches
RESET LOAD IA0 - 4 5
OA0 - 4
5
5:32 Decoder
TQ8032
CNTRL LVL
The TQ8032 is a non-blocking 32 x 32 digital crosspoint switch capable of 800 Megabits per second per port data rates. Utilizing a fully differential internal data path and ECL I/O, the TQ8032 offers a high data rate with exceptional signal fidelity. The symmetrical switching and noise rejection characteristics inherent in differential logic result in low jitter and signal skew. The TQ8032 is ideally suited for digital video, data communications and telecommunication switching applications. The non-blocking architecture uses 32 fully independent 32:1 multiplexers (see diagram on page 2), allowing each output port to be independently programmed to any input port. The switch is configured by sequentially loading each multiplexer's 5-bit program latch (OA0:4) with the desired input port address (IA0:4) and enabling the LOAD pin. When complete, the CONFIGURE pin is strobed and all new configurations are simultaneously transferred into the switch multiplexers. Data integrity is maintained on all unchanged data paths.
Typical output waveform with all channels driven
Features
* >25 Gb/s aggregate BW * 800 Mb/s/port NRZ data rate * Non-blocking architecture * 500 ps delay match * Differential ECL-level data I/O; Selectable CMOS/TTLlevel control inputs * Low jitter and signal skew * Fully differential data path * Double buffered configuration latches * 196-pin CQFP package
Electrical Characteristics
Min
Data Rate/Port Jitter Channel Propagation Delay Ch-to-Ch Propagation Delay Skew 800 150 2300 500
Max
Units
Mb/s ps pk-pk ps ps
Applications
* Telecom/Datacom Switching * Hubs and Routers * Video Switching
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1
SWITCHING PRODUCTS
32 5-Bit Program Latches
TQ8032
Figure 1. Architecture
32 X 1-BIT MULTIPLEXER
. . . . . .
DATA IN 0 (I0)
32 X 1-BIT MULTIPLEXER
Input Buffers
. . . . . .
DATA IN 15 (I15)
. . . . . .
Output Buffers .
.
. .
DATA OUT 31 (O31) DATA OUT 0 (O0)
DATA IN 16 (I16)
Input Buffers
. . . . . .
DATA IN 31 (I31) CONFIGURE RESET LOAD 5:32 5 DECODE OUTPUT SELECT ADDRESS (OA0:4) Configuration Register Program Register
5
5
INPUT ADDRESS (IA0:4)
Table 2. Pin Descriptions
Signal
I0 to I31, NI0 to NI31 O0 to O31, NO0 to NO31 IA0:4
Name/Level
Data input true and complement. Differential ECL Data output true and complement. Differential ECL Input address. CMOS/TTL
Description
Differential data input ports. Differential data output ports. Input port selection address that is written into the selected output port program latches (OA0:4). IA4 IA3 IA2 IA1 IA0 Input port 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 : : : : : : 1 1 1 1 1 31 Output port selection address. Selects the output port program latches to which the input port selection address (IA0:4) is written. OA4 OA3 OA2 OA1 OA0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 : : : : : 1 1 1 1 1 Output port 0 1 2 : 31
OA0:4 CMOS/TTL
Output select address.
2
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TQ8032
Figure 2. Package Pinout
O0 NO0 GND O1 NO1 O2 NO2 GND O3 NO3 O4 NO4 GND O5 NO5 O6 NO6 GND O7 NO7 CTRL LVL VCC (+5V) VEE (-5V) RESET GND NI7 I7 GND NI6 I6 NI5 I5 GND NI4 I4 NI3 I3 GND NI2 I2 NI1 I1 GND NI0 I0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
VCC (+5V) O8 NO8 GND O9 NO9 O10 NO10 GND O11 NO11 O12 NO12 GND O13 NO13 O14 NO14 GND O15 NO15 O16 NO16 GND O17 NO17 O18 NO18 GND O19 NO19 O20 NO20 GND O21 NO21 O22 NO22 GND O23 NO23 O24 NO24 GND O25 NO25 VEE (-5V)
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 06 97 98
Top View 196-Pin Package
NOTE: All unmarked pins are not connected.
196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148
VEE (-5V) I8 NI8 I9 GND NI9 I10 NI10 I11 GND NI11 I12 NI12 I13 GND NI13 I14 NI14 I15 GND NI15 I16 NI16 I17 GND NI17 I18 NI18 I19 GND NI19 I20 NI20 I21 GND NI21 I22 NI22 I23 GND NI23 I24 NI24 I25 GND NI25 I26 NI26 VCC (+5V)
Table 2. Pin Descriptions (continued)
Signal
LOAD CONFIGURE RESET
Name/Level
Description
CMOS/TTL Enables the selected output port program latches while set `high'. Latches the data when set to a 'low' level. CMOS/TTL CMOS/TTL Transfers the program latches data to the configuration latches and implements the switch changes while set "high." Latches the data when set to a "low" level. Puts the switch into Broadcast or Pass-Through configuration, overwriting existing configurations. Broadcast mode: All output ports are connected to data input port 0. This mode is selected by applying a RESET "high" pulse with CONFIGURE held "low." Pass-through mode: I0 is connected to O0, I1 to O1, etc. This mode is selected by applying a RESET "high" pulse with CONFIGURE held "high." Selects the input levels for the input address (IA0:4), output address(OA0:4), CONFIGURE, LOAD and RESET inputs. Inputs are configured for TTL when tied to GND and CMOS when left unconnected.
CNTRL LVL
Input level control. GND/Open
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3
SWITCHING PRODUCTS
147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99
VEE (-5V)
GND I27 NI27 I28 NI28 GND I29 NI29 I30 NI30 GND I31 NI31 IA(4) IA(3) GND IA(2) IA(1) IA(0) CONFIG GND LOAD OA(4) OA(3) OA(2) GND OA(1) OA(0) NO31 O31 GND NO30 O30 NO29 O29 GND NO28 O28 NO27 O27 GND NO26 O26
VCC (+5V)
TQ8032
Table 3. Absolute Maximum Ratings5
Symbol
TSTOR TCH TC VCC VEE VTT VIN IIN VIN IIN VOUT IOUT PD
Parameter
Storage Temperature Junction (Channel) Temperature Case Temperature Under Bias Supply Voltage Supply Voltage Load Termination Supply Voltage Voltage Applied to Any ECL Input; Continuous Current Into Any ECL Input; Continuous Voltage Applied to Any TTL/CMOS Input; Continuous Current Into Any TTL/CMOS Input; Continuous Voltage Applied to Any ECL Output Current From Any ECL Output; Continuous Power Dissipation per Output POUT = (GND - VOUT) x IOUT
Absolute Max. Rating
-65 C to +150 C -65 C to +150 C -65 C to +125 C 0 V to +7 V -7 V to 0 V VEE to 0 V VEE -0.5 V to +0.5 V -1.0 mA to +1.0 mA -0.5 V to VCC +0.5 V -1.0 mA to +1.0 mA VEE -0.5 V to +0.5 V -40 mA 50 mW
Notes
1 2 3 3 4
4
Notes: 1. 2. 3. 4. 5.
For die applications. TC is measured at case top. All voltages specified with respect to GND, defined as 0V. Subject to IOUT and power dissipation limitations. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device's performance may be impaired and/or permanent damage to the device may occur.
Table 4. Recommended Operating Conditions4
Symbol
TC VCC VEE VTT RLOAD JC
Parameter
Case Operating Temperature Supply Voltage Supply Voltage Load Termination Supply Voltage Output Termination Load Resistance Thermal Resistance Junction to Case
Min
0 4.5 -5.5
Typ
Max
85 5.5 -4.5
Units
C V V V
Notes
1,3
-2.0 50 2
2 2
C/W
Notes: 1. 2. 3. 4.
TC measured at case top. Use of adequate heatsink is required. The VTT and RLOAD combination is subject to maximum output current and power restrictions. Contact the Factory for extended temperature range applications. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed, singularly or in combination, the operating range specified.
4
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TQ8032
Table 5. DC Characteristics1,2 - Within recommended operating conditions, unless otherwise indicated.
Symbol
VIH VIL IIH IIL VICM VIDIF VIH VIL IIH IIL VOCM VODIF VOH VOL IOH IOL ICC IEE
Notes:
Parameter
ECL Input Voltage High ECL Input Voltage Low ECL Input Current High ECL Input Current Low ECL Input Common Mode Voltage ECL Input Differential Voltage (pk-pk) CMOS/TTL Input Voltage High CMOS/TTL Input Voltage Low CMOS/TTL Input Current High CMOS/TTL Input Current Low ECL Output Common Mode ECL Output Differential Voltage ECL Output Voltage High ECL Output Voltage Low ECL Output Current High ECL Output Current Low Power Supply Current (+) Power Supply Current (-)
Min
-1100 VTT
Max
-500 -1500 +30 -30
Units
mV mV A A mV mV V V A A mV mV mV mV mA mA mA mA
Test Cond.
Notes
VIH = -0.7 V VIL = -2.0 V
-1500 400 3.5/2.0 0/0
-1100 1200 VCC/VCC 1.5/0.8 +100 -100
2 2 VIL = 0 V 2
-1500 600 -1000 VTT 20 0
-1100 -600 -1600 27 8 20 -1950
1. Test conditions unless otherwise indicated: VTT = -2.0 V, RLOAD = 50 to VTT. 2. Input level is selected by the CNTRL_LVL input. Tieing CNTRL_LVL to GND selects TTL levels, leaving CNTRL_LVL OPEN selects CMOS levels.
Table 6. AC Characteristics1 - Within recommended operating conditions, unless otherwise indicated.
Symbol
Jitter T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 TR,F Channel Progagation Delay Channel-to-Channel Delay Skew CONFIG to Data Out (Oi) Delay LOAD Pulse Width CONFIG Pulse Width IAi to LOAD High Setup Time LOAD to IAi Low Hold Time OAi to LOAD High Setup Time LOAD to OAi Low Hold Time Load to CONFIG RESET Pulse Width Output Rise or Fall Time 7 7 0 3 0 3 0 10 300 400
Parameter
Maximum Data Rate/Port
Min
Typ
Max
800 150 2300 500 5
Units
Mb/s ps pk-pk ps ps ns ns ns ns ns ns ns ns ns ps
Notes
1,2 1
3
Notes: 1. Test conditions: VTT = -2.0 V, RLOAD = 50 to VTT; ECL inputs: VIH = -1.1 V; VIL = -1.5 V; CMOS inputs: VIH = 3.5 V, VIL = 1.5 V; ECL outputs: VOH -1.0 V, VOL -1.6 V; ECL inputs rise and fall times 1 ns; CMOS inputs rise and fall times 20 ns. A bit error rate of 1E - 13 BER or better for 223 - 1 PRBS pattern, jitter and rise/fall times are guaranteed through characterization. 2. 800 Mb/s Non-Return-Zero (NRZ) data equivalent to 400 MHz clock signal. 3. Rise and fall times are measured at the 20% and 80% points of the transition from VOL max to VOL min.
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5
SWITCHING PRODUCTS
VIH = VCC
2
TQ8032
Figure 3. Timing Diagram - Switch Configuration
RESET
Input Address Output Address
LOAD T4 T10 CONFIGURE T8 T6 Data1 In T1 Data1 Out OA OB OC OD Invalid Data Out DA DB DC T7 T9 DD DE T3 OE OF OG DF DG T5
Note:1 No data loss on nchanged data paths
Notes: 1. No data loss on unchanged paths.
Figure 4. Timing Diagram - Reset
RESET T11 CONFIGURE Output Data Broadcast T3 Pass-through
Notes:
1. LOAD input must remain LOW to insure correct programming of the switch. 2. "Broadcast" is defined as data input 0 to all data outputs (0..31). 3. "Pass-through" is defined as data input 0 to data output 0, data input 1 to data output 1, etc.
6
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TQ8032
Typical Performance Data
Figure 5. Jitter - Single Channel
250 Vee = -5.0 V, Tc = 40 C 200
Jitter (ps)
100 p-p 50 rms 0 0 0.2 0.4 0.6 0.8 1
Data Rate (Gb/s)
Figure 6. Output Delay
2.50
Output Delay (ns)
Vee = -5.0 V, Vin = 900 mV p-p 2.25 2.00 1.75 1.50 -60 -30 0 30 60 90 120
Case Temperature (C)
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7
SWITCHING PRODUCTS
150
TQ8032
Figure 7. Mechanical Dimensions Bottom View (marking up)
CHIP CAPACITOR, 4 PLACES
50
Top View (marking down)
49
CL
1
PIN 1 INDEX
196
LID
TQ8032-M XXXX YYWW
0.011 PIN WIDTH CL 0.450 .0025
148 98 99 147
A
A
0.675 0.600 .0035 0.775 .003
LOT CODE
DATE CODE
Section A-A
.060 HEAT SPREADER DEVICE
1. Part is symmetrical about the center axes. 2. Centerline bisects center pin in both directions. 3. See pad detail below. 0.025 centers 0.015 CL 0.010
.125
SEATING PLANE .064
0.715 CL
0.088
Ordering Information
PAD LAYOUT DETAIL
TQ8032-M
Additional Information
800 Mb/s 32x32 ECL Crosspoint Switch
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
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The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
8
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